Communications system for receiving and transmitting data cells

ABSTRACT

A communication system comprising a hub slot adapted to receive any one of a plurality of hub cards for receiving and transmitting data cells; a plurality of universal card slots; a plurality of interface cards insertable in any one of the plurality of universal card slots for receiving incoming ones of the data cells containing data and transmitting outgoing ones of the data cells containing data; an add bus having respective data links connected between individual ones of the universal card slots and the hub slot for receiving the outgoing ones of the data cells from the plurality of interface cards and transmitting the outgoing ones of the data cells to the hub slot; a drop bus having a single data link connected between all of the universal card slots and the hub slot for transmitting the incoming ones of the data cells from the hub slot to the plurality of interface cards; and an arrangement within each of the interface cards for filtering the incoming ones of the data cells from the drop bus and thereby routing the data cells to an appropriate one or more of the plurality of interface cards.

FIELD OF THE INVENTION

This invention relates in general to digital communication systems, andmore particularly to a novel switching system using asynchronoustransfer mode (ATM) transmission and switching of information.

BACKGROUND OF THE INVENTION

The emergence of high-speed asynchronous transfer mode (ATM)communications is a recent result of the diverse demands now being madeon enterprise backbone networks. Early enterprise networks weredominated by voice traffic with only a relatively small amount ofcircuit bandwidth devoted to data and other applications. More recently,a range of new applications has evolved resulting in significant changesto existing backbone networks. High-bandwidth video telephony and videoconferencing, for example, are rapidly becoming essential requirementsin digital communication systems. Similarly, the bandwidth requirementsfor LAN (Local Area Network) interconnection across multiple sites isalso increasing as established prior art LAN systems such as Ethernet™and Token Ring are upgraded to meet the demands of faster communicationand more sophisticated processing.

For example, Fibre Distributed Data Interface (FDDI) LANs operating at100 Mbps are presently being deployed while even higher bit rates LANtypes are emerging as a result of text-based personal computers beingreplaced by multi-media work stations and associated servers. Typically,multi-media work stations and their associated servers support documentarchitectures that comprise not only text but also high resolution stillimages and moving images with sound. Thus, instead of inter-site LANtraffic being dominated by file transfers of textual information as inthe prior art, LAN file transfers in newer systems are migrating towardshigher volume, high bit-rate mixed-media traffic.

The combined effect of such developments has necessitated thedevelopment of a more flexible method for the allocation of transmissionbandwidth in order to efficiently utilize inter-site leased circuitsassociated with enterprise networks.

The developments discussed above are not limited to private networks,but are occurring in public carriers as well.

In order to meet these new demands in private and public digitalcommunication systems, an international standard operating mode has beendeveloped for use with broadband integrated services digital networks(BISDN) based on the asynchronous transfer mode (ATM) of transmissionand switching. The aim of the ATM protocol is to provide a more flexiblefacility for the transmission and switching of mixed-media trafficcomprising data, voice, still and moving images and video.Traditionally, constant bit rate traffic such as voice has beentransmitted and switched using pre-assigned time slots, whereas data isnormally transmitted in the form of variable length frames which aremultiplexed together on a statistical basis. According to the ATMprotocol, transmission and switching is performed on fixed-sized unitsreferred to as "cells". Cells from different sources (eg. voice, data,video, etc.), are multiplexed together on a statistical basis fortransmission purposes.

Each standard ATM cell is 53 bytes in length, comprising a 48-byteinformation field (also referred to as the "payload"), and a five-byteheader containing routing and other fields.

Like packet and frame switching, ATM operates on a virtualcall/connection basis. This means that prior to any user informationcells being sent, a virtual connection is first placed through thenetwork. During this phase, a virtual connection identifier (VCI) isassigned to the call at each interexchange link along the route. Theassigned identifier, however, has only local significance to a link andchanges from one link to the next as the cells relating to a connectionpass therethrough. This means, therefore, that the routing informationcarried in each cell header can be relatively small.

In particular, each incoming link/port has associated therewith arouting table that contains the corresponding output link/port and a newVCI to replace the incoming VCI for the subsequent link/port. Therouting of cells in both directions along a predetermined route istherefore extremely fast as it involves only a simple look-up operation.As a result, cells from each link can be switched independently and atvery high rates. This allows parallel switch architectures to be usedand high-speed circuits (ie. in the gigabit-per-second range), eachoperating at its maximum capacity.

In practice, the VCI is made up of two sub-fields: a virtual pathidentifier (VPI) and a virtual channel identifier (VCI). The VPI fieldrelates to statically assigned connections whereas the VCI field relatesto dynamically assigned connections. Routing can be performed using oneor the other, or a combination of the VPI and VCI subfields. Forexample, a virtual path may be set up through the network on asemi-permanent basis (by network management) between each pair ofnetwork endpoints. The cells relating to multiple (ie. concurrent) callsbetween these end points are then multiplexed together and then routedalong the same assigned path. In this example, therefore, the routing ofcells within the network is performed using the VPI field and the VCIfield would be used at the end point to relate cells to a particularcall.

The ATM reference model defines three protocol layers, as follows: (1)ATM adaptation layer which overlies the (2) ATM layer which overlies the(3) physical layer.

The ATM adaptation layer (AAL) provides a range of alternative serviceclasses for performing an adaptation function between the class ofservice provided to the user (e.g. for the transport of data framesbetween two LANs), and the cell-based service provided by the ATM layer.

The ATM layer provides the required multiplexing of cells relating todifferent connections into a single stream of cells, and the subsequentdemultiplexing of the cell streams. The ATM layer also effects therequired routing/relaying of cells based )ria the VPI and/or VCI fields.

The physical layer interfaces with the particular transmission mediumwhich carries the actual cells (eg., fibre optic, coaxial cable, etc.),and may be implemented via a number of different communicationtechnologies depending on the type of transmission being used (eg.plesiochronous or synchronous). For the former, the transmitterestablishes a frame structure over the bit/byte stream that exactlymatches the ATM cell. The receiver then processes the incoming bytestream on a byte-by-byte basis until a valid 5-byte cell header isformed. The incoming byte stream is then processed on these fixed cellboundaries. In the case of a synchronous link (e.g. OC3/STM1), the framepayload field is not a multiple of the cell size and hence the cellboundaries will change from one frame to the next. With this type oflink, therefore, a pointer in the overhead channels is used to identifythe start of the first cell boundary in the payload field while celldelineation is performed based on the HEC byte (discussed in greaterdetail below).

As discussed above, the ATM layer performs all of the functions relatingto the routing and multiplexing of cells over virtual connections whichmay be semi-permanent or set up on demand. For the latter, a signallingprotocol is implemented which is similar to that used with ISDN.

There are two different header formats for standard ATM cells commonlyreferred to as UNI and NNI. Each format incorporates a VPI field as thefirst byte. However, for the format used over a user-network access linkintended for use by user devices that generate and receive cellsdirectly, the four most significant bits of the first header byte arereplaced by a generic flow control (GFC) field that has only localsignificance over the link and is included to allow cells to beallocated different priorities. This field is not present within thenetwork, however, and instead the VPI field is extended across theentire byte.

The second byte of the header comprises a first nibble which is anextension of the VPI field. Thus, for the format used over auser-network access link, the VPI, field is eight bits, whereas withinthe network the VPI field is twelve bits. The least significant fourbits in the second byte of header information comprises a first portionof the VCI field. The third byte of the header continues the VCI fieldand the first four most significant bits of the fourth byte of theheader complete the VCI field. Thus, the VCI field in a standard ATMheader consists of sixteen bits. The four least significant bits of thefourth header byte include (1) a payload type (PT) field which is usedto enable cells relating to the C and M planes associated with the ATMreference model to be differentiated from cells containing userinformation, and (2) a cell-loss priority (CLP) bit. The CLP bit is usedto allow a user to indicate those cells associated with a connectionwhich should be discarded first. This is useful because an ATM networkoperates by multiplexing on a statistical basis so that it is possiblefor cell buffers to overflow within an exchange.

Finally, a header error control (EC) field is provided as a variation ofan eight-bit cyclic redundancy check (CRC) polynomial for detectingerrors in the header. If the CRC polynomial fails, the cell isdiscarded. However, for single-bit errors, hardware may be provided tocorrect the error based on information from the HEC field.

There are a number of areas in the design of existing ATM-basedcommunications systems where substantial improvements may be made insignal routing efficiency, diagnostic support and hardwaresimplification.

Firstly, it is desirable to provide a system which can flexiblyaccommodate a variable number of interface circuits per switch fabricinterface, depending on interface card bandwidth. Prior art systems havebeen provided with fixed bandwidth for each interface card within suchsystems.

Secondly, while the virtual connection identifier (VCI) may be used toestablish routing of a cell from link-to-link on a point-to-point basisor "shared" front one point to several destinations (i.e.point-to-multipoint), it can only do so at the expense of costly andcomplex circuitry. Similarly, only a rudimentary level of cell priorityqueuing is possible using standard ATM cell headers. Also, according tomany prior art systems, intershelf communication has been via parallelbusses which are of inherently low speed and low bandwidth. Therefore,there is a need for inexpensive enhanced routing capability of ATM cellsboth inter-node and intra-node within such communications systems.

Thirdly, since cell streams in an ATM communication system areessentially point-to-point and terminate in queuing points, there isnormally no need to maintain synchronous timing throughout the switchingfabric. However, since some interface cards require a standard timingreference, it is desirable to maintain system timing in such a system.The standard method for maintaining intra-node system synchronization inan asynchronous serial link (eg. intershelf link), is to run asynchronous timing link throughout the system. However, such systemssuffer from jitter transfer problems resulting from synchronouslyregenerated timing signals due to instability of chaining phaselocked-loops (PLL).

Alternatively, some prior art systems maintain synchronization byproviding a dedicated timing wire from the system synchronization unit(SSU) to all timing destinations. This effectively restricts thelocation of the SSU to a predetermined slot in the system which isspecifically wired to receive it.

Accordingly, there is a need to maintain system synchronization withoutextra timing wires and without suffering from loss of sync and otherproblems inherent in prior art PLL synchronization systems.

Fourthly, in prior art systems debug access to the operating software inthe system is provided by a special software load with debugging codebuilt in, and a dedicated hardware debug port must be provided ontowhich debug equipment must be attached in order to gain access to thedebug software. It is desirable to provide a system in which the debugsoftware is always in place and in which the development system supportcommunications are integrated into the ATM fabric.

Finally, it is desirable to provide system redundancy for improvedreliability of critical system functions.

Other opportunities exist for the improvement of ATM communicationssystems design, such as in the areas of control communications, queueservicing algorithms, node synchronization architecture, etc.

SUMMARY OF THE INVENTION

According to the present invention, an improved ATM communicationssystem is provided the design of which has been directed by the desireto address the prior art problems discussed above.

Firstly, the maximum utilization of the switching core is achieved inthe system of the present invention by providing a variable number ofUniversal Card Slots (UCS) per Inter Shelf Link (ISL), depending on theinterface card bandwidth. For example, a large number of low-speed UCScards may be provided in one embodiment, while fewer high-speed UCScards may be provided in another embodiment, and in each case switchingcore efficiency may be optimally maintained.

Secondly, with respect to the problem of routing ATM cells within thecommunication system, according to the present invention a plurality ofoverhead bytes are pre-pended to the standard 53 byte ATM cell in orderto facilitate cost-efficient cell routing on a point-to-point basis or apoint-multipoint basis within the system, with cell priority queuing,simplified egress statistics gathering, and error detection across thepre-ended bytes and the four bytes of the ATM header (with the HEC fieldomitted).

Thirdly, with respect to the problem of maintaining systemsynchronization, according to the present invention an 8 Khz timingsignal is embedded in Ordered Sets (discussed in greater detail below)which are transported over the ISLs and can appear anywhere in a"Supercell" framing structure (the concept of a "Supercell" is discussedin greater detail below). Therefore, the timing signal is independent ofany serial data clock, as contrasted with prior art synchronous systems.No special jitter reducing circuitry or wiring is required, and thetiming source and SSU can be located anywhere within the switchingfabric to which the ATM cells may be directed, in contrast with priorart synchronization systems using a dedicated timing wire.

Fourthly, with respect to development system support, according to thepresent invention an integrated real-time development system is providedwherein the debug software is permanently installed in the system and inwhich the development system support communications are integrated intothe ATM fabric, such that the prior art requirement for special debugequipment at a customer site is minimized, if not entirely eliminated.

Finally, the system architecture of the present invention allows forswitch fabric redundancy.

BRIEF DESCRIPTION OF THE DRAWINGS

A detailed description of the preferred embodiment is provided hereinbelow with reference to the following drawings, in which:

FIG. 1 is a block diagram of an exemplary digital communication systemimplementing the method and apparatus of the present invention;

FIG. 2 is a block diagram showing the cell switching core in greaterdetail connected to an exemplary peripheral shelf of the systemillustrated in FIG. 1;

FIG. 3 is a diagram of the modified ATM cell format for point-to-pointcommunication, according to a first embodiment of the invention;

FIG. 4 is a diagram showing the modified ATM cell format forpoint-to-multipoint communication, according to a second embodiment ofthe invention;

FIG. 5 shows a card address format according to the preferredembodiment;

FIG. 6 is a block diagram of an interface circuit for connection to auniversal card slot and to external signal carrying media, includingcircuitry for generating and filtering the proprietary ATM header dataaccording to the preferred embodiment;

FIG. 7 is a block diagram of a switching ASIC used on a hub card of theperipheral shelf shown in FIG. 2;

FIG. 8 is a block diagram showing a cell queuing core of the ASIC shownin FIG. 7;

FIG. 9 is a block diagram of a standard interface ASIC in the interfacecircuit of FIG. 6 for receiving and transmitting formatted ATM cells toand from the switching fabric;

FIG. 10 is a flowchart showing operation of a receive filter in theinterface circuit of FIG. 9;

FIG. 11 is a flowchart showing details of a multicasting cell sortingprocedure in the flowchart of FIG. 10;

FIG. 12 is a flowchart showing operation of a first filter sortingalgorithm in the flowchart of FIG. 10;

FIG. 13 is a flowchart showing operation of a second filter sortingalgorithm in the flowchart of FIG. 10;

FIG. 14 is a functional schematic diagram of an intershelf linkaccording to the present invention; and

FIG. 15 is a block diagram showing distribution of timing informationthrough the communication system of FIGS. 1 and 2, according to thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

With reference to FIG. 1, a block diagram is provided of a switchingarchitecture for implementing the method and apparatus of the presentinvention in accordance with one embodiment. The system comprises a cellswitching core, 1 connected to a plurality of interface card access orperipheral shelves 3A, 3B, etc., via respective 800 Mbps inter-shelflinks (ISL) 5. In the present disclosure, the terms "access shelf" and"peripheral shelf" will be used interchangeably throughout. In amulti-shelf access arrangement such as shown with reference to blocks 3Dand 3E, a further ISL 5A may be provided directly between the accessshelves. Furthermore, in some system "stand-alone" configurations, asingle interface card peripheral shelf may be provided without therequirement of a cell switching core 1. Alternatively, a multi-shelfaccess arrangement such as shown with reference to blocks 3D and 3E maybe provided in stand-alone configuration with a switching circuitincorporated directly into each peripheral shelf.

All external interfaces (e.g. OC-3, video, FDDI, etc.) terminate oninterface cards located in twelve universal card slots (UCS) located oneach peripheral shelf 3B, 3C and/or 3D, as discussed in greater detailbelow with reference to FIG. 2. In the multi-shelf access arrangement 3Dand 3E, up to ninety-six (96) universal and slots may be provided foreach inter-shelf link (ISL) 5. Furthermore, according to the presentinvention the number of UCS interface cards sharing an ISL may be madevariable depending on the interface card bandwidth. For example, a largenumber of low-speed UCS cards may be provided in one embodiment (eg.3D), while fewer high-speed UCS cards may be provided in anotherembodiment (eg. 3B). This flexibility provides better utilization of thecell switching core 1 and provides more control of statistical gain.

Each 800 Mbps ISL 5 is adapted to transmit ATM cells between the cellswitching core 1 and associated ones of the access shelves 3A, 3B, etc.using either electrical or optical, full duplex, fibre channel (FC-0 andFC-1 only) interfaces, in a well known manner.

Turning to FIG. 2, the cell switching core 1 is shown functionally Asproviding inter-shelf cell switching for respective ones of the accessshelves 3A, 3B, etc. The switching core 1 uses an input cell filteringand output queuing architecture to implement a cell space switch (i.e.cells can be switched to any output from any input). In the preferredembodiment, the switching core 1 can range from 2 to 256 ISL ports persystem. Therefore, the maximum switching capacity is 256 ISL/system×800Mbps/ISL=204.8 Gbps/system. The cell switching core 1 incorporates aplurality of dual switching cards (such as 1A, 1B and 1C shown in FIG.15). Each such dual switching card has access to the switching core 1,and provides two output ISLs 5 for connecting up to two peripheralshelves 3A, 3B, etc.

In FIG. 2, a representative peripheral shelf 3C is shown connected tothe switching core 1 via respective ISLs 5. As discussed above, theperipheral shelf 3C incorporates twelve universal card slots (UCS) 22for receiving respective interface cards 21 for implementing allinterface (ie. between the switching fabric and the outside world viaI/O interfacing to optical, coax, or other physical medium), control andresource functions. For the purpose of describing the present invention,the terms "interface card" and "UCS card" may be used interchangeably.Each peripheral shelf, such as the shelf 3C shown in FIG. 2, includestwo special purpose hub cards (only one hub card 23 being shown for easeof illustration), which form part of the entire switching fabric. Theswitching fabric of the preferred embodiment is fully duplicated forredundancy. Accordingly, one hub card is provided for each half of thefully duplicated switching fabric. The hub card 23 is releasablydisposed in a hub slot 24, and multiplexes and concentrates cells frommultiple interface cards 21 onto the 800 Mbps intershelf links (ISLs 5)connected to the switching core 1. Each UCS 22 housing an interface card21 has a 200 Mbps interface to the hub card 23, designated as an add bus25. As discussed above, the hub card 23 terminates an ISL 5 from theswitching core 1 and drives a further 800 Mbps shared bus on thebackplane, this bus being designated as the drop bus 27 from which theUCS cards 21 filter received ATM cells. The hub card 23 also includes aloop-back circuit 29 which is normally provided for diagnostic purposes.However, in a stand-alone configuration of the access or peripheralshelf 3C, the loop-back 29 can be used for directing the 800 Mbps datawhich is concentrated front the add bus 25 back to the 800 Mbps drop bus27.

The system has a duplicated ATM switching fabric for fault tolerance.The major components of the switching fabric are the hub cards 23,switching shelf 1, and the ISL cables 5. The interface cards 21 putcustomer data onto both fabrics.

According to a further possible stand alone configuration of theperipheral shelf 3C, the switching core 1 may be effectivelyincorporated into the peripheral shelf itself where two or more suchperipheral shelves with internal switch core are connected together(such as peripheral shelves 3D and 3E connected via ISL 5A in FIG. 1).The number of ports connected to the switching core 1 can be madeflexible (eg. a large number of low bandwidth ports may be added) tofully utilize, available bandwidth.

Interfaces which require greater than 200 Mbps of system switchingcapacity are interfaced directly with the switching core 1 viaassociated ISLs 5 (e.g. high speed interface 3A in FIG. 1).

As discussed in greater detail below, according to the present inventiondata on each of the aforementioned 800 Mbps links (ie. ISLs 5, dropbusses 27, etc.) is assembled as a succession of "Supercells", eachcomprising an Ordered Set (ie. 32 bit longword aligned data structurefor control information) followed by 128 60-byte proprietary ATM cells.The use of these supercells results in straightforward cell delineationand supports a simple protocol for relaying various types of systemlevel status information.

In operation, for simplified data flow in the aforementionedstand-alone, configuration of the peripheral shelf 3C (i.e. withoutrouting through the switching core 1), each UCS or interface card 21provides the appropriate line termination, performs AAL/ATM layerprocessing of received data, adds additional routing information to theATM cell to create a formatted cell header in accordance with theprinciples of the present invention, and sends the formatted cells tothe hub card 23 over the 200 Mbps add bus 25. As discussed in greaterdetail below, the formatted cell of the present invention has sevenadditional overhead bytes pre-pended to the standard 53 byte ATM cell,to form a 60 byte formatted cell.

For 800 Mbps peripheral shelves 3C, the hub card 23 multiplexes andconcentrates the formatted cells from the individual UCS cards 21 ontoan 800 Mbps cell stream which is looped back via the aforementionedembedded switching core (not shown), or via the loop-back 29 to all ofthe UCS slots 22 on the common drop bus 27. For other than 800 Mbpsperipheral shelves, the loop-back function may or may not be providedinternally on the hub card 23. Each interface card 21 filters the cellsfrom the 800 Mbps drop bus 27 using the routing information which wasadded to the cell header, queues the cells, performs AAL/ATM layerprocessing on the transmitted data and drives the associated lineinterfaces via the interface card 21.

For data flow through a larger node which uses switching core 1, thesystem operates in an identical manner as discussed above in connectionwith a small node except that instead of looping back the data to thedrop bus 27 through the embedded switching core or loop-back 29 of hubcard 23, the 800 Mbps cell stream is encoded within hub card 23 with an8B10B code (as per fibre channel FC-1 standard) mild converted to a 1Gbaud serial stream which is then sent to the switching core 1 via ISL5. The cell stream is received by switching core 1 and the cells withinthe ISL 5 are routed to the proper ISL outputs of switching core 1.

The hub card 23 on the appropriate peripheral shelf (e.g. shelf 3C,etc,), receives the cell stream from the switching core 1 via ISL 5 andin response drives the 800 Mbps shared drop bus 27 on the backplane ofthe peripheral shelf. Then, as discussed above in connection with thesmaller node interconnection, each UCS housing an interface card 21filters the cells from the 800 Mbps drop bus 27 using the routinginformation that was added to the cell header, queues the cells,performs AAL/ATM layer processing on the transmitted data and drives theassociated line interface via the interface card 21.

The configuration of add bus 25 and drop bus 27 results in a "star bus"topology which provides unique advantages over the prior art in theimplementation of a high speed communication system. It is known thathigh speed data transmission is most easily accomplished withpoint-to-point transmission lines. Therefore, by splitting the add bus25 into a plurality of point-to-point links in the present invention,significant advances are made over prior art conventionalpoint-to-multipoint architectures (e.g. using multi-party bi-directionalbusses). Such prior art systems suffer from the following problems:

low impedance and discontinuous transmission lines due to card loading

difficult line terminations

high speed busses requiring parallel terminations that consumesignificant power

the effective speed at which the busses can operate is limited byfactors such as arbitration for bus mastership.

The point-to-point communication provided by the add bus 25 in thestar-bus topology of the present invention overcomes these problems.

In the "drop" direction (i.e. drop bus 27) since all the UCS cards 21are required to receive all of the incoming data cells, a unidirectionalbus 27 is utilized. Since the bus 27 is unidirectional, the topology ofthe present invention benefits from simple transmission line terminationrequirements.

According to the present invention, proprietary overhead information isadded to the standard 53 byte ATM cell in order to assist in the routingof the cells through the switching fabric. The cell format of thepresent invention is used on all links between various cards of thesystem. This includes the links from the UCS cards to the hub card 23,links to and from the switching core 1, and from the hub card 23 to theUCS cards 21.

As discussed above, in accordance with the preferred embodiment, sevenbytes are pre-pended to the standard 53 byte ATM cell in order to form a60byte formatted cell. The additional header information is used touniquely address any "port" on any UCS housing an interface card 21 andto identify the priority of the attached ATM cell. The additional headerinformation is also used to support a multi-casting capability where theaddress field identifies a group of UCS interface ports. Use of theadditional header information pre-pended to the standard ATM cell allowsfor improved cell routing over prior art ATM-based switching systems.Unused bits in the header may be used for other control functions (eg.providing signalling information at the discretion of software).

As discussed in greater detail below, there are two cell types definedby the additional header information according to the principles of thepresent invention, as follows: (1) point-to-point; and (2)point-to-multipoint.

Sending cells to a specific card within the system requires that thecells be routed to the drop bus 27 to which the particular UCS interfacecard 21 is connected. The card then must filter the cells destined forit from the remaining cells present on the drop bus 27.

When a cell is addressed to a particular UCS interface card 21, the dropbus 27 that the particular card "listens" to is referred to as a"terminal bus" (i.e. the data on the bus is not routed to a subsequentbus). If, on the other hand, a cell is addressed to a card that is partof the switching fabric, the bus that is "listened" to by that card maybe an intermediate bus whose data is routed to other buses. Inaccordance with the present invention, the definition of the routing ofthe cell through the fabric is identical in both cases. As discussed ingreater detail below with reference to FIG. 9, circuitry is provided ineach UCS interface card 21 for filtering the cells on the monitored busin order to recognize correct cells destined for the particular card.

FIG. 3 illustrates a formatted ATM cell in accordance with the presentinvention, for implementing point-to-point communication. The fieldspre-pended to the standard ATM cell are defined in Table A below.

It should be noted that for all field definitions throughout thisdisclosure, bits are assumed to be transported in the order of left toright and top to bottom. In multi-bit fields, the most significant bitis transported first.

                  TABLE A                                                         ______________________________________                                        Field                                                                         Name    Description                                                           ______________________________________                                        MT      When this bit is low the cell is considered to be an                          empty cell. The CRC value is checked to determine if                          any bit errors occurred, otherwise the cell is discarded                      without any processing being done.                                    Pt-Pt   Indicates addressing is either for a point-to-point or for                    a point-to-multipoint connection. "1" = point-to-point;                       "0" = point-to-multipoint.                                            NCT     Newbridge Cell Type. These bits are used by the                               interface ASIC to determine if the cell is part of the                        normal data stream or if it should be routed to the                           internal control or RDS queues.                                       RFU     Reserved for Future Use. These bits should be set to                          "0" to guarantee compatibility with future                                    implementations which may use them.                                   Priority                                                                              Indicates cell priority. Supports 8 priorities. "000" =                       Lowest Priority; "111" = Highest Priority.                            AAL5    Identifies this cell as being part of an AAL5 frame.                  Source  Indicates the cell's ingress port. Range: 1 . . . 3. Zero is          Port    illegal.                                                              Stage 1/                                                                              These fields each allow the selection of one output out               Stage 2/                                                                              of sixteen from a switching shelf, with the capability of             Stage 3 having three stages of switching shelf. This permits the              Address construction of exceptionally large switching systems.                Card    This field uniquely identifies a destination element                  Address within an ISL.                                                        Egress  This field is set on ingress on the cell relay cards and              Connection                                                                            identifies the connection at the egress point. It is used             Identifier                                                                            for performing address translation and statistics                             gathering on egress. It permits the transmission of an                        identifier which is easier and more economical to use                         when updating statistics than the entire VP/VC field of                       the ATM address.                                                      Port    Used by multi-port interface cards to address a port                          (from up to sixteen). In cells sent to the switching                          fabric this field is RFU.                                             NCC     Newbridge Communications Channel. This 4-bit will                             provide for information exchange between cell                                 processing elements in a switch node. Preliminary use                         may include bits for local switch congestion indication.              CRC - 8 Cyclic Redundancy Check. Provides error detection for                         the combined Newbridge and ATM header. The                                    polynomial used is x.sup.8 + x.sup.2 + x.sup.1 +1.                    ______________________________________                                    

As indicated in Table A, the card address field is used to select adestination element within an ISL. One possible definition of this fieldin shown in FIG. 5, although other addressing definitions are possible.

                  TABLE B                                                         ______________________________________                                        Field Name                                                                             Description                                                          ______________________________________                                        Range #  The Range number identifies the type of card, and the                         range of locations to which the address applies. It is                        encoded in the following format:                                              0000 - UCS Shelf #1, Interface ASIC #1                                        0001 - UCS Shelf #2, Interface ASIC #1                                        0010 - UCS Shelf #3, Interface ASIC #1                                        0011 - UCS Shelf #4, Interface ASIC #1                                        0100 - UCS Shelf #5, Interface ASIC #1                                        0101 - UCS Shelf #6, Interface ASIC #1                                        0110 - UCS Shelf #7, Interface ASIC #1                                        0111 - UCS Shelf #8, Interface ASIC #1                                        1000 - UCS Shelf #1, Interface ASIC #2                                        1001 - UCS Shelf #2, Interface ASIC #2                                        1010 - UCS Shelf #3, Interface ASIC #2                                        1011 - ALL Hub Cards                                                          1100 - UCS Shelf #1, Interface ASIC #3                                        1101 - UCS Shelf #2, Interface ASIC #3                                        1110 - UCS Shelf #3, Interface ASIC #3                                        1111 - ALL DSC Cards                                                          In this format, Ranges 0-7 correspond to the UCS cards                        in shelves 1-8. Ranges 8-15 are slightly more                                 complicated.                                                         Location #                                                                             The Location # identifies a unique location with a range.                     It is encoded in the following format:                                        UCS Ranges: (Ranges 0-10, 12, 13, 14)                                       3  2  1  0                                                                    Slot #                                                                        Slot # 0-15 identify the peripheral shelf slots 1-16.                         HUB Ranges: (Range 11)                                                        3  2  1  0                                                                    Shelf #   X/Y                                                                 Shelf #0-7 identify the chained shelf numbers 1-8.                            X/Y identifies the fabric with 0 = X, 1 = Y                                   DSC Ranges: (Range 15)                                                        3  2  1  0                                                                    RFU  Stage #  X/Y                                                             RFU, set = 0 until defined.                                                   Stage #0-2 identifies the switching stage 1-3, with                           (stage #3 is an RFU)                                                          X/Y identifies thc fabric with 0 = X, 1 = Y.                           ______________________________________                                    

Transmitting cells which are part of a point-to-multipoint connectionrequires that the cell be routed to every drop bus 27 which has a cardthat is part of the multi-cast group. The cell must also contain amulti-cast identifier that each card checks to determine if the card ispart of the predetermined multi-cast group for the cell. This group canthen be used to determine which ports of the UCS cards are to use thecell (ie. which interface cards 21 are to receive the data).

The cell format of a point-to-multipoint cell is given in FIG. 4. Thefield definitions are provided in Table D below.

                  TABLE C                                                         ______________________________________                                        Field                                                                         Name     Description                                                          ______________________________________                                        MT       When this bit is low the cell is considered to be an empty                    cell. The CRC value is checked to determine if any bit                        errors occurred, otherwise the cell is discarded without                      any processing being done.                                           Pt-Pt    Indicates addressing is either for a point-to-point or for a                  point-to-multipoint connection. "1" point-to-point; "0" =                     point-to-multipoint.                                                 NCT      Newbridge Cell Type. These bits are used by the                               interface ASIC to determine if the cell is part of the                        normal data stream or if it should be routed to the                           internal control or RDS queues.                                      RFU      Reserved for Future Use. These bits should be set to "0"                      to guarantee compatibility with future implementations                        which may use them.                                                  Priority Indicates cell priority. Supports 8 priorities. "000" =                       Lowest Priority; "111" = Highest Priority.                           RFU      Reserved for Future Use. These bits should be set to "0"                      to guarantee compatibility with future implementations                        which may use them.                                                  Switch Shelf                                                                           A multicast cell may be routed to multiple drop busses.              Output Bitmap                                                                          This is accomplished by bit mapping the output ports of                       the switching shelf that the cell is to take.                        Multicast                                                                              This field is set on ingress on the cell relay card and              Group    identifies a system wide unique Multicast Group.                     Connection                                                                    Identifier                                                                    AAL5     Identifies this cell as being part of an AAL5 frame.                 Source Port                                                                            Indicates the cell's ingress port. Range: 1 . . . 3. Zero is                  illegal.                                                             NCC      Newbridge Communications Channel. This 4-bit will                             provide for information exchange between cell                                 processing elements in a switch node. Preliminary use                         may include bits for local switch congestion indication.             CRC - 8  Cyclic Redundancy Check. Provides error detection for                         the combined Newbridge and ATM header. The poly-                              nomial used is x.sup.8 + x.sup.2 + x.sup.1 + 1.                      ______________________________________                                    

The cell header describes a number of different cell types includingdata cells, control cells and RDS cells. This allows control and RDScommunications to be carried in-band within the data switching fabric.Many systems use an out-of-band control channel which restricts thecontrol card to a specific location in the system. Allowing the controland RDS communications to be carried in-band within the data switchingfabric allows scalability to very high bandwidths and increasesreliability. In-band communications means that no special hardware orsoftware is required at the local site and debugging can be doneremotely.

Turning now to FIG. 6, the functional blocks of a representative UCSinterface card 21 are illustrated. The illustrative example shown inFIG. 6 is an OC-3/STM-1 interface card for connection to a peripheralshelf 3B, 3C, 3D or 3E (FIG. 1). Interface cards which are appropriatefor implementing a high speed interface or an 800 Mbps interface may bedevised using similar functional elements as shown in FIG. 6.

As discussed above, the basic function of the OC3/STM-1 UCS interfacecard 21 is to transport ATM cell data between the switching fabric andthe SONET/SDH network link. The blocks required to perform this functionmay be identified as follows:

(1) Control/status block 71;

(2) Synchronization block 73;

(3) Backplane interface block 75;

(4) ATM block 76;

(5) SONET/STM-1 block 77; and

(6) Transport medium and interface block 78.

The control/status block 71 provides coordination of interface functionsand establishes node control communication via the backplane interfaceblock 75.

The synchronization block 73 accepts and/or generates a systemsynchronization reference, as discussed in greater detail below. Thisblock generates timing signals required for all functional blocks of theUCS card 21, including the provision of timing signals whereby theSONET/STM-1 transmission meets predetermined jitter and accuracyrequirements if a Synchronization Unit (SU) is located on the UCS card21.

The backplane interface block 75 processes the specially formatted ATMcells (ie. ATM cells having additional pre-pended bytes) that aretransmitted to and from the switching fabric, and provides dataintegrity checking, connectivity checking and conversion of cellsbetween the specially formatted ATM cells and standard ATM cells. Thefunctional requirements for this block are discussed in greater detailbelow with reference to FIG. 9.

The ATM block 76 processes the ATM cells that pass between the backplaneinterface block 75 and the SONET/STM-1 block 77, including VPI/VCImapping, usage parameter control (UPC) policing, and per VPI/VCIstatistics gathering. ATM block 76 comprises an ingress ATM logic block76C, an egress ATM logic block 76A, an ingress UPC 76B and ingressmicroprocessor context memory interface 76D.

The ingress ATM logic block 76C or Ingress Cell Controller (abbreviatedas ICC) provides the following ATM layer functionality: (1) VPI/VCIaddress compression, (2) cell counters, (3) OAM control cell processing,(4) OAM cell extraction, and (5) prepending of the seven header octetsto the ATM cell (FIGS. 3 and 4). A 64K×16 SRAM 1702 provides the ICCwith per connection OAM functionality and VPI/VCI compression tables.

There is a global bit located in the ICC 76C which is programmed uponinitialization to signal an internal address compression block whetherthe link is UNI or NNI. When the link is UNI, an 8 bit VPI and 16 bitVCI is compressed to 12 bits. When the link is NNI, a 12 bit VPI and 16bit VCI is compressed to 12 bits (referred to herein as ICI).

The 12 bit resultant ICI allows the OC-3 Card to support up to 4K ofconnections using any VPI and a VCI within the range of 0 to 4095.

When a cell is received, the VPI is used to index a VP Table. The resultis a 16 bit word which determines if this VPI has been enabled andwhether it's a VPC or VCC. If the connection is VPC, the VP Table entryalso contains a 12 bit ICI. If the connection is VCC, the VP Tablecontains a VC Table pointer ani a VCI Mask. The VC Table pointer pointsto one of 17 2K VC Sub Tables. The VCI Mask is used to determine howmany of the VCI bits will be used to index the VC Sub Table. This maskmust be either 11 or 12. The OC-3 doesn't support any other maskselections. The unused VCI bits are compared to zero. If they containnon-zero values, the cell is considered invalid and the appropriateactions occur. Otherwise, the VC Sub Table entry contains an ICI for theVC connection.

Once ICI has been generated, it is used to point into the ICC's contextmemory 76D. A bit is checked to verify validity of the connection. If itisn't a valid connection, ICI is ignored, the ingress UPC 76B is advisedthat it has an invalid cell and the connection's VPI/VCI values arestored into the ICC memory's Invalid Table. If the connection isenabled, ICI is passed to the ingress UPC 76.

The memory accessed by ingress UPC 76B is the 64K×32 memory 76F residingon the ingress UPC's host port. This memory provides the ingress UPCwith; UPC information, per connection statistics, NATM header octets(ie. internal Newbridge ATM cell formats in accordance with Tables A andD), and VPI/VCI translation bytes.

The Context Table within memory 76F contains 4K data structures. Eachdata structure represents information for a VP or VC switchingconnection. The UPC table contains 1.5×4K (6K) data structures whicheach represent the necessary information for a bucket.

NATM header registers are provided as memory locations in 76F whichcontain the seven octets representing the NATM header. These fields areprepended to the beginning of the cell header for use throughout theswitching fabric. Included within these fields are port addresses, ECI(Egress Connection Identifier), MGI (Multicast Group Identifier) etc.

The SONET (Synchronous Optical Network)/STM-1 block 77 adapts the ATMcells received from and transmitted to the OC-3/STM-1 physical layer,and provides overhead processing for the section, line and path layers.It also provides line (egress) and diagnostic (ingress) loop backcapability. More particularly, the SONET/STM-1 interface block 77provides both an 8-bit 19.44 Mhz and a serial 155 Mhz access to theTransport Medium Interface 78 and 8-bit 25 Mhz access to the ATM block76. Multiple serial interfaces are also provided for an optional NNImodule.

The interface block 77 also provides (either directly or via the NNImodule) full access to SONET/STM-1 framing information and providesfour-deep receive and transmit FIFOs (not shown) for the ATM layerinterface 76. It also delineates ATM cells and provides HEC checking andcorrection.

The transport medium interface 78 provides optical (or coax) interfaces,clock recovery and data timing between an optical medium 79 such asfibre optic cable (or coax medium 79A). The transport medium interface78 also provides electro-optical conversions required to pass the ATMcells to and from the optional OC-3/STM-1 link. The functionalrequirements for transport medium interface block 78 are discussed ingreater detail below.

For signal flow in the egress direction, the backplane interface block75 monitors the type of formatted ATM cells, and discriminates betweendata, RDS, control and empty cells. The cell type is determined by itsNCT and MT bits (see FIGS. 3 and 4).

Data cells are passed by the backplane interface 75 to the ATM block 76.The destination address of each active cell is checked before the cellis passed to the ATM block. The egress ATM logic 76A strips off theseven formatted ATM cell header octets from each active cell beforepassing it to the interface 77. The seven formatted ATM cell headeroctets are generated and added to each cell received in the ingressdirection by ingress ATM logic 76C, before transmission to the switchingfabric, as discussed in greater detail below.

The RDS and control cells are not transmitted to the ATM block 76.Instead, these cells are stored for use by the control/status block 71.In the ingress direction, RDS and control cells are created by thecontrol processor 71A and inserted into the ingress ATM cell stream fortransmission through the switching fabric.

Empty cells passing in the egress direction through backplane interface75 are discarded. In the ingress direction, a nibble is added to thecell to indicate the start of a cell. If there are no cells to betransmitted to the switching fabric, the link remains idle.

In the egress direction, multicast cells are received and used to lookup an enable bit in a multi-cast look-up table (discussed in greaterbelow with reference to FIG. 10). If a match occurs, the cell isaccepted; otherwise, it is discarded. Furthermore, point-to-point cellsin the egress direction are received and compared to a pair of filterregisters (discussed in greater detail below with reference to FIGS. 12and 13). An exact match is required for the cells to be accepted.Otherwise, the cells are discarded.

Cells passing in the egress direction are placed in one of four priorityqueues. CLP discard can be enabled and is performed when a programmablediscard threshold is matched or exceeded. These queues also provideforward congestion notification if enabled through the PTI bit field ofthe ATM header. The ASIC incorporated into backplane interface 75(discussed in greater detail below with reference to FIG. 9) providesstatistics for the number of cells arriving (16 bit); the numb er ofcells discarded CLP=0 (16 bit ); the number of cells discarded withCLP=1 (16 bit) and the number of cells arriving congested (16 bit).Status flags are also available for full and empty queues; discard stateand congested state.

The backplane interface 75 also provides a variety of maintenancefeatured. Firstly, by defining invalid point-to-point filters for thecell comparison, the control processor 71A is capable of detectingincorrect destination addresses of cells passing through the backplaneinterface 75 in the egress direction. Also, a loop back function may beprovided to the loop ingress path entering the backplane interface block75 to the egress data path exiting the backplane block. This provides ameans to test the ATM block 76 and SONET/STM-1 block 77 during power updiagnostics.

It is necessary for the control/status microprocessor 71A to access thememory 1702 in order to initialize and "rip down" connections. Insteadof using a dual port memory architecture, the ICC 76C directly controlsthe memory. Whenever the microprocessor 71A requires access to thememory, it tells the ICC what it wants to do, and the ICC executes thenecessary instructions on behalf of the microprocessor 71A. This way theICC 76C knows when it isn't using the memory during a cell time and canallot that time for the microprocessor interface 1703.

In addition, the backplane interface 75 is capable of declaring certainalarm conditions. As discussed above, redundancy is provided by means ofduplicated drop busses in each peripheral shelf 3A, 3C, etc. Each of thetwo drop busses provides a loss of clock indicator for the egress cellscoming from the switching fabric. A hardware indicator is active when notransition has been detected on the interface clock for 140 nanoseconds.This time is derived from 14 clock cycles of the C 100 M clock utilizedby the ASIC discussed below with reference to FIG. 9. The UCS cardsoftware monitors ATM receive clock failures for the redundant ATMswitch fabrics. The UCS card software provides an alarm indication whenthis failure is alarmed on the active ATM interface.

The UCS card hardware also monitors the level of the four queues for theegress cells received from the switching fabric. In the event that thebuffer fills, the event is counted and aggregated as a statistic value.

According to the preferred embodiment, ATM cell processing is performedby means of a pair of application specific integrated circuits (ASICs)within the switching core 1, hub cards 23 and UCS cards housinginterface cards 21. The first ASIC is shown in FIG. 7 for performing adual purpose switching function. In one application, the circuit of FIG.7 is used in hub cards 23 of the access shelves 3B, etc., formultiplexing the 200 Mbps data on add bus 25 into a single 800 Mbps cellstream for application to inter-shelf links 5. In the secondapplication, the circuit of FIG. 7 is utilized in the switching core 1to filter (i.e. switch) a pair of 800 Mbps input cell streams into asingle 800 Mbps output stream. The 800 Mbps output stream can then beshared by multiple additional ASICs of the form shown in FIG. 7 toprovide filtering (i.e. switching) of the same 800 Mbps output link frommultiple input links in the switching fabric.

In the "multiplex mode" of operation, six input processors 81 receiverespective 200 Mbps signal streams from respective UCS cards housinginterface circuits 21. Thus, by using two of the switching andmultiplexing circuits of FIG. 7, the desired functionality of the hubcard 23 may be implemented for concentrating twelve 200 Mbps cellstreams carried by the add bus 25 into a single shared 800 Mbps outputstream. Each 200 Mbps input data stream is processed via a respectiveprocessor 81 for cell delineation and for CRC checking. The add buslinks 25 from the UCS cards to the hub card 23 consist of a data nibble(i.e. 4 bits) and clock signal only, so that cell delineation may beperformed based on a simple algorithm which recognizes cells beingpreceded by a unique start-of-cell nibble, or other suitable technique.

Each of the format converter/multiplexers 83 gathers the three 200 Mbpsstreams output from processor 81 and converts them to a single 800 Mbpsinput stream for further processing by a cell queuing core 85. The cellqueuing core 85 is discussed in greater detail below with reference toFIG. 8. A pair of multiplexers 86 respectively select one of either the800 Mbps input (switching mode) or the three 200 Mbps cell streamsoutput from format converter/multiplexer 83 (multiplex mode) for inputto the cell queuing core 85. Thus, the system provides sufficientflexibility to have one of the 800 Mbps inputs to the cell queuing core85 configured as three 200 Mbps inputs (ie. multiplexer mode) while theother 800 Mbps input is configured as a direct 800 Mbps input (ie.switch mode).

Slot monitor FIFO 87 provides a microprocessor interface to "monitor" aspecific 200 Mbps input or a specific 800 Mbps input from themultiplexers 86. The circuit of FIG. 7 captures a cell from theappropriate input link when so directed via the microprocessor port. Themicroprocessor then directly reads the full 60 byte formatted ATM cellfrom FIFO 87.

The cell queuing core 85 is shown in greater detail with reference toFIG. 8 comprising 800 Mbps processing blocks 91 which perform clockdetection, link termination, CRC checking and cell filtering functions.When an 800 Mbps input stream to the cell queuing core 85 is sourcedfrom three 200 Mbps inputs (ie. multiplex mode) the cell filteringfunction of processors 91 is typically disabled. This allows all cellsin the input streams to be queued. As per the 200 Mbps inputs, each 800Mbps input can be enabled or disabled from having their respective cellsenter queue memory 93.

Memory manager 95 controls four cell queues within memory 93, forproviding a total of 256 cells of queuing space which can be flexiblyallocated between the four queues. Memory manager 95 operates on thedata contained within the four queues to process each cell in accordancewith all aspects of the ATM cell header, including CLP discard and PTIcongestion notification.

An arbitration control 97 provides information on the current state ofthe cell queues to an external arbiter (not shown). When multiplecircuits share the same 800 Mbps output link, the external arbiter isrequired to decide which circuit source is the next cell and at whichpriority. The arbitration control 97 provides the external arbiter withall of the necessary information required to implement any queue servicealgorithm which can be downloaded and is reconfigurable at any time.

The output formatter 98 creates a formatted 800 Mbps link (as well asinserting the appropriate priority cell when so instructed by theexternal arbiter), in the form of a "supercell", as discussed in greaterdetail below.

Insertion FIFO 99 is provided to allow control and real-time developmentsystem (RDS) cells to be transmitted onto the 800 Mbps output link.Details of the RDS functionality are provided below. As discussed ingreater detail below, the interface circuit of FIG. 9 provides astandard RDS and control interface to the local microprocessor. Thecircuit of FIG. 7 provides an interface to the circuit of FIG. 9 totransmit these control/RDS cells onto the 800 Mbps output port. The 800Mbps input processors 91 contain a plurality of registers which are usedfor cell filtering. Specifically, point-to-point and point-to-multipointcell filtering is accomplished using internal "mask" and "value"registers against which input values may be compared and must be matched(or alternatively masked) in order for a point-to-point orpoint-to-multipoint cell to enter an internal queue from the 800 Mbpsinterface. In this regard, all cell filtering in the system of thepresent invention is conducted via pattern matching.

Before turning to FIG. 9, a brief description is provided herein of theRDS (Real-Time Development System) functionality of the ATM switchingsystem according to the present invention.

RDS is used extensively in the system according to the presentinvention, to develop and debug software. Debugging can take place in arange of environments from a development lab to a customer site where itcan be used on live equipment without impacting service or customerdata. As discussed below, the RDS function of the present inventionoperates in an event mode and in a command mode.

RDS events are embedded in the actual software at development time andin most cases are not subsequently removed for two reasons: (1) eventscan assist in tracing subsequent problems, (2) taking them out wouldaffect the real time execution of code, which may have real functionaleffects, even though the code has been designed so as to not besensitive to execution speed.

An RDS event is simply a set of writes to an RDS event port, embedded inthe software at significant software interfaces and points of interest.The data that is written to the port includes an event identifier and avariable length sequence of data bytes that define what software eventis occurring. It is similar in concept to putting a "print" statementwith the software to indicate that this portion of code is executing andusing the print data to indicate exactly what is happening.

In the ATM switching system, RDS events are generated by nearly all ofthe processors in the system and the event data is placed on the ATMswitching fabric along with control messaging and customer data. Toreduce the amount of bandwidth consumed on the ATM switching fabric, theASIC (FIG. 9) contains a hardware filter that can discard RDS eventsbased on the event identifier. In normal operation of the ATM switchingsystem according to the present invention, all of the events generatedby all the processors in the system are discarded using the hardwarefilter of the ASIC in FIG. 9.

The events can be enabled onto the switching fabric by changing thestate of these hardware filters. This can be done selectively for eachinterface ASIC (FIG. 9) in the system and for each of the 256 eventsthat the ASIC supports. This allows someone with knowledge of the RDSevents in the system to enable selective events to aid in diagnosis ofproblems.

RDS events can be displayed on a VT100 terminal or a workstation.Generally an additional card is installed into the system for filteringthe RDS events off the switching fabric and formatting them for displayon the VT100 or workstation. The ATM cells that carry the RDS event dataindicate the source address and using this knowledge, the eventidentifier and the event data, text can be formatted and displayed onthe VT1100 terminal or workstation that corresponds to the event whichhas occurred in the software. The control card of the ATM switchingsystem is also capable of filtering the RDS event cells and formattingis them for display. This allows remote debugging of a live system sinceaccess to this control card is available across the network.

Since the events are left in the code, the priorities of code design areto keep the size of the event code to a minimum, to keep the processingload of event generation to a minimum, and to ensure that the properevents are within the code to allow the diagnosis of problems andvisibility into the operation of the system.

As discussed above with reference to FIGS. 3 and 4, the contents of theheader field of the cell are completely programmable, including the ATMheader VCI/VPI fields. The CRC header protection field is calculated andinserted into the cell header automatically, and a two byte field isprovided for a RDS source address to be used by the receiving end toidentify the source of the cell. As discussed in greater detail below,an address mapped set of registers that store the fields of the cellheader are provided in the interface ASIC of FIG. 9. This allowsmodifications to be made to portions of the header field withoutre-writing the whole header each time a small change is needed, (e.g.priority changes). With control over the ATM VCI/VPI fields, event cellscan be routed directly out of the switching system as true ATM cells toa destination outside the node, without having to be relayed by thecontrol complex or an RDS card. This feature allows event cells to betransmitted to a remote debug location directly, assuming that aconnection to the network is available. However, it should be noted thatthe pre-pended bytes of FIGS. 3 and 4 (including the NCT bits) are lostwhen the cell exits the node, but this information is not usually neededif the receiving entity is expecting only RDS event cells.

In command mode, RDS is used to actively debug processors in the systemby allowing source and assembly level debugging as well as memory readand write operations. According to this mode of operation, a hostgenerates one or more RDS command cells, each comprising a commandidentifier and a variable length identifier for defining the command, toa target system. The target system responds by returning to the host anRDS event cell containing the results. The commands are very simple (eg.read memory at a given address, write memory to a given address withprovided data, identify target processor type, return values of targetprocessor registers, etc.) Using these simple command operations, thehost system is capable of constructing an advanced functionality such assource level debugging, assembly level debugging, breakpoint insertionand stack tracing, etc.

When an RDS command cell is filtered off of the backplane by aninterface ASIC (ie. the ASIC shown in FIG. 9), it queues the cell andgenerates a high priority non-maskable interrupt to the target processoron the associated card. The use of a non-maskable interrupt allows theRDS system in the command mode to reliably interrupt the targetprocessor so that other interrupt handlers on the card can even bedebugged using the RDS.

Since both RDS command and RDS event cells conform to standard ATM cellformat in accordance with the present invention, these cells can betransmitted across an ATM network so that an RDS host processor canremotely debug a target processor by operating in a remote mode. Theingress interface circuitry (FIG. 6) of the system containing the targetprocessor causes the cell type (NCT) to be set to RDS Command for RDScommand cells arriving on the VP/VC (FIG. 6).

Turning now to FIG. 9, a functional block diagram is provided of theinterface ASIC which performs ATM backplane functions required for anycard to interface with the switching fabric. As such, the circuit ofFIG. 9 is intended for any interface, hub or switching card thattransmits and receives ATM cells through the system, such as the UCSinterface card 21 discussed above with reference to FIG. 6.

In order to send cells into the switching fabric, the circuit of FIG. 9provides a receive link interface 100 in the form of an externally timedinterface for formatted ATM cells to be transmitted on the add bus 25.This receive link interface 100 operates at a maximum of 400 Mbps,although the maximum add bus rate is 200 Mbps, as discussed above.

The completely formatted ATM cells received from a UCS (or other) cardvia receive link 100, are applied to the add bus 25 via add businterface/header protector 101 along with an inserted CRC-8 byte in theATM HEC field. As discussed above with reference to FIG. 6, the UCS cardassembles completely formatted cells using the header fields shown inFIGS. 3 and 4, except for the CRC-8 byte. The CRC-8 byte covers theseven octet (ie. byte) overhead as well as the four remaining octets ofthe standard ATM header.

Control cells and RDS cells can be applied to the add bus 25 throughFIFOs 102 and 104 which are accessible through a microprocessorinterface 106.

The circuit of FIG. 9 provides a separate interface for each of theredundant drop buses 27. For each drop bus 27, the circuit monitors fora loss of clock and for CRC errors on all cells, via drop busframing/CRC check circuits 108. The signals output from circuits 108 aremultiplexed at 110 and applied to a receive cell filter 112.

The received cells from the active fabric are then filtered via receivecell filter 112 to determine which cells are addressed to the associatedinterface circuit 21. Control/RDS cells and user data cells are filteredusing the predefined Card Address field (i.e. the fourth byte in thepoint-to-point cell format of FIG. 3) to facilitate interface cardredundancy, as discussed in greater detail below. Multi-cast cells areverified against entries in an external, 64K connection, multi-castlook-up table 116, also discussed in greater detail below.

Turning to FIG. 10, the receive cell filtering process executed byfilter 112, is shown in detail. Upon receipt of a formatted ATM cell(step 124), empty cells are identified and discarded (step 126).Identification of empty cells is accomplished by checking the MT bit inthe first octet of the formatted ATM header. Next, the Pt--Pt bit isqueried to determine whether the ATM cell is formatted forpoint-to-point or point-to-multipoint addressing (step 128). Addressfiltering is then split into multi-cast and point-to-point portions ofFIG. 10.

For multi-cast cells, the Multi-cast Group Identifier field is used tolook up an enable bit in a multi-cast look-up table (MCLT) stored withinan external RAM 116, discussed in greater detail below. If a matchoccurs (step 130), the cell is accepted. Otherwise, the cell isdiscarded (step 127). Accepted cells are then sorted according to theNewbridge Cell Type (NCT) field in the header (step 132).

Turning briefly to FIG. 11 in conjunction with Table E below, themulti-cast cell sorting step 132 is shown in greater detail.

                  TABLE E                                                         ______________________________________                                        NCT                Cell Type                                                  ______________________________________                                        00                 User data                                                  01                 Control                                                    10                 RDS Command                                                11                 RDS Event                                                  ______________________________________                                    

Upon receipt of a multi-cast cell (step 134), the NCT bits are analyzedto identify an RDS Command, User Data, and Control or RDS Event (step136). In response, sorting is continued on the basis of the cell beingidentified as either an RDS Cell (step 138), a Control Cell (step 140)or a User Data Cell (step 142).

Returning to FIG. 10, the identified RDS Cells, Control Cells and UserData Cells are then accepted by the filter 112, as represented by steps144, 146 and 148.

For point-to-point cells, the Card Address field of the expanded ATMheader is compared against the contents of two internal filterregisters, hereafter referred to as F1 and F2. An exact match isrequired against the filter register contents before a cell is deemed tohave passed the filter function. Cells which do not match F1 or F2 arediscarded (steps 150, 152 and 127).

Control cells can be required to match F1, F2, or either F1 or F2 beforebeing accepted. User Data Cells pass through an identical stage. Thisallows the Control Cells to be filtered off of one address, for example,the physical card address, and the User Data Cells to be filtered off ofother addresses, for example, the physical card address of the redundantcard. This also allows the User Data Cells (and/or the Control Cells) tobe filtered off of either F1 or F2. This permits cells addressed toeither card of a redundant pair to be accepted by both. RDS Cells areaccepted only of the match F1.

Details of the sorting and filtering procedure for F1 and F2 matchedpoint to-point cells are shown in FIGS. 12 and 13, respectively.

Once a point-to-point cell has matched F1 (step 150) it is then sortedby the expanded ATM header information (step 154). With reference toFIG. 12, upon receipt of the point-to-point (PP) cell (step 156), theNewbridge Cell Type is identified using the criteria set forth in TableE, above (step 158). RDS Command Cells are accepted (step 160). ControlCells and RDS Event Cells are accepted if the Control Filter Selectfield (CFS[1:0]) in an internal filter select register of filter 112 isprogrammed to accept F1 passed cells. The CFS bit field is shown inTable F, below. Control and RDS Events cells will therefore be acceptedif the CFS bit field is "10" or "11" (steps 162 and 164).

                  TABLE F                                                         ______________________________________                                        CFS (1:0)          Cell Filter Selected                                       ______________________________________                                        00                 Undefined                                                  01                 Filter 2                                                   10                 Filter 1                                                   11                 Filter 1 or Filter 2                                       ______________________________________                                    

User Data Cells are accepted if the User Filter Select field (UFS[1:0])in the Filter Select Register is programmed to accept F1 passed cells(steps 166 and 168). The UFS bit field is shown below in Table G. UserData Cells will therefore be accepted if the UFS bit field is "10" or"11". If either a Control Cell or a User Data Cell fails to pass eitherF1 or F1+F2, then the cell is discarded (step 170).

                  TABLE G                                                         ______________________________________                                        UFS (1:0)         Cell Filter Selected                                        ______________________________________                                        00                Undefined                                                   01                Filter 2                                                    10                Filter 1                                                    11                Filter 1 or Filter 2                                        ______________________________________                                    

Once a point-to-point (PP) cell has matched F2 (step 152), it is thensorted by the expanded ATM header information (step 171). With referenceto FIG. 13, upon receipt of the point-to-point (PP) cell (step 172), theNewbridge Cell Type is identified using the criteria set forth in TableE, above (step 174). RDS command cells are discarded (step 176). ControlCells and RDS Event Cells are accepted if the Control Filter Selectfield (CFS[1:0]) in the internal filter select register of filter 112 isprogrammed to accept F2 passed cells. The CFS bit field is shown inTable F, above. Control and RDS Events cells will therefore be acceptedif the CFS bit field is "01" or "11" (steps 178 and 180).

User Data Cells are accepted if the User Filter Select field (UFS[1:0])in the Filter Select Register is programmed to accept F2 passed cells(steps 182 and 184). The UFS bit field is shown below in Table G, above.User Data Cells will therefore be accepted if the UFS bit field is "01"or "11". If either a Control Cell or a User Data Cell fails to passeither F1 or F1+F2, then the cell is discarded (step 176).

The interface ASIC of FIG. 9 stores multicast lookup tables in the sameexternal RAM 116 that is used for queue memory. The first 2K×32 block ofmemory, from address 0 to 800 hex, is reserved for this purpose. Thelookup tables are used when a multicast cell arrives, to determine ifthe multicast group is destined for the particular card. To accomplishthis, the 16-bit Multicast Group Identifier in the expanded ATM headerof the cell is used to address a single bit of the multicast block ofexternal memory. The 16-bit identifier is translated into ani 11-bitaddress to access the 2K block of external memory, and a 5-bitidentifier to select which bit of the 32-bit wide data word to choose.This bit, a yes/no indicator of the validity of the multicast cell tothis ASIC, is used when processing incoming cells. A "0" in the memorylocation indicates that the multicast cell is valid, and a "1" indicatesthat the multicast cell is invalid. When no external RAM 116 is used(which may occur in bypass mode), the data pins of the external RAMcontroller 118 may be tied to a logic high (eg. "1") level, so that allmulticast cells outside the internal lookup range will be discarded.Alternatively, the data pins may be wired to present a logic low (ie."0") value when a multicast "read" is performed, so that all cells areaccepted.

An internal lookup feature is supplied for the use of an interface ASICwithout external RAM 116. The uppermost 32 bits of the external memorymulticast block are transparently mapped to an internal 32-bit memory.This enables a subset of the multicast capabilities for cards that haveno external RAM. User access of the 32-bit internal field istransparent; it is accessed through the microprocessor as if it were inexternal RAM. The 32-bits of external RAM are permanently mapped over.

Receive cells which have been filtered by Receive Cell Filter 112 arethen sent to the designated receive queues via queue manager 114. Userdata cells are queued in external memory 116, through a 1.5 Gbps memoryinterface 118. The queue manager 114 of the preferred embodimentsupports up to 4096 cells of external storage. RDS command cells aresent to the RDS cell FIFOs 104 for access through the processor port106. Control cells and RDS event cells are sent to the internal sixteencell FIFO 102 for access through the processor port 106. The operationand flow of RDS command cells, control cells and RDS event callsdiscussed in greater detail below.

Receive queuing to transmit link interface 120 can be bypassed (i.e.queue manager 114 can be disabled for receive cells). This allows thecircuit of FIG. 9 to function as a receive cell filter for an externalcell queuing device. However, the RDS and control cells are nonethelesssent to the internal FIFOs 102 and 104, if so enabled.

Finally, the receive cells are sent out the transmit link interface 120,under control from an external clock (TXLINKCLK).

The circuit of FIG. 9 services the priority "3" queue via queue manager114 if it contains a cell, and then the priority "2" queue and so ondown to priority "0". However, this feature may be over-ridden via thetransmit link arbitration port 122. This port provides an indication ofa cell arrival, with the cell priority, to the aforementioned externalarbiter (not shown). In return, the external arbiter can force thecircuit of FIG. 9 to service a given priority queue for the next cell,regardless of whether a higher priority queue is currently non-empty.

The 800 Mbps Inter-Shelf Link (ISL 5) is the common mechanism forconnecting all component shelves together in the system of the presentinvention. The ISL is a high-speed serial link which uses the lowerlayers of the Fiber Channel specification to transfer digital signalsbetween access shelves 3A, 3B, etc., in a multi-shelf accessarrangement, and between switching core 1 and the access shelves 3A, 3B,etc. As discussed above, each hub card 23 generates proprietary"supercells" for transmission along the ISLs 5 and drop bus 27 usingFibre Channel technology. Specifically, the output formatter 98 (FIG. 8)of the switching ASIC cell queuing core 85 (FIG. 7), generatessupercells in accordance with the concept of an Ordered Set, asdiscussed in greater detail below. A representative ISL 5 is shown inFIG. 14 comprising a high speed parallel to serial converter (IX 151),equalization circuitry 153, connectorization 155, physical transportmedia (eg. shielded pair copper wires or optical fiber), receivercoupling 156, termination 157, and a high speed serial to parallelconverter (RX 158). The 8B/10B code requires a 1 Gbaud line rate inorder to support the 800 Mbps data rate on the link. The physicaltransport media for the Fiber Channel interface can be either electricalor optical.

One of the features of the 8B/10B encoding scheme is the ability tocommunicate special command characters over the serial link. The K28.5code is a particularly special command character in that it is used bythe receiver 158 to establish byte and word synchronization.Additionally the K28.5 character is used within the system of thepresent invention for cell delineation and optionally for the transportof the 8 Khz system synchronization signal, as discussed in greaterdetail below.

The Fiber Channel specification introduces the concept of an OrderedSet. An Ordered Set (OS) is a four byte grouping, composed of the K28.5character and three additional data bytes. Ordered Sets can be sent overthe ISL 5 by asserting a special signal on the Fiber Channel transmitdevice 151, and their presence is detected at the receiver 158 by theassertion of a OS indication signal.

An ordered set is defined as shown in Table H.

                  TABLE H                                                         ______________________________________                                        Bit 31-Bit 24                                                                          Bit 23-Bit 16                                                                             Bit 15-Bit 8 Bit 7-Bit 0                                 ______________________________________                                        OS Type  K28.5       Drive & Scan Byte                                                                          RFU                                         Bitfield Special Character                                                                         (SOS only)                                               ______________________________________                                    

The second byte is always the K28.5 special character. The first byte isa field of 8 bits for encoding the various OS types. Since an OS may beconsidered to signal an event or status condition, each condition isassigned one bit in the field (as shown in Table I) which is set toindicate the relevant event or status condition, allowing a single OS toencode numerous types of OS "events". These conditions are notnecessarily mutually exclusive--for instance, an OS with a first byteequal to 05H would indicate both an SOS and an STOS.

                  TABLE I                                                         ______________________________________                                        Bits 7-3        Bit 2    Bit 1     Bit 0                                      ______________________________________                                        RFU             STOS     ETOS      SOS                                        Reserved For Future Use                                                                       System   Extracted Supercell                                                  Timing   Timing    OS                                                         OS       OS                                                   ______________________________________                                    

The Drive & Scan field is only used if the OS Type Bitfield's SOS bit isasserted. Otherwise, it is treated as a "don't care" field. Uponreception of an SOS, the switching ASIC of FIGS. 7 and 8 will latch theDrive & Scan byte in an internal register of the 800 Mbps inputprocessors 91. For transmission of an SOS, the output formatter 98 (FIG.8) derives the value of its Drive & Scan byte from an internal register.This provides out-of-band communication from one switching ASIC throughthe Fiber Channel to the next downstream switching ASIC.

An Idle Ordered Set is defined by all bits in the OS Type Bitfieldhaving the value 0. RFU bits are set to zero by default.

The Inter-Shelf Link makes use of Fiber Channel technology and thenotion of a "supercell" to aid in cell delineation. As indicated above,a supercell consists of a Supercell Ordered Set (SOS) followed by 12860byte proprietary ATM cells.

The Supercell format is shown below in Table J.

                  TABLE J                                                         ______________________________________                                                Bit Number                                                            Word      15             8      7       0                                     ______________________________________                                        0         OS Type Bitfield  K28.5                                             1         Drive & Scan byte RFU                                               2 to 3,841                                                                              128 × 60 Byte Newbridge cells                                 ______________________________________                                    

Supercells are used on the Fiber Channel ISLs 5 and the local dropbusses 27, as well as internally in certain cards. The presence of anyOrdered Set is always indicated by some sort of Ordered Set Indication(OSI) signal. The 8 Khz timing signal is carried on these same FiberChannel links and local drop busses via the supercells. The two TimingOrdered Sets, ETOS and STOS (Table I), are used to distribute timinginformation through-out the system, as discussed in greater detailbelow. They may therefore occur at any time, even in the middle of asupercell or ATM cell.

Each switching ASIC (FIG. 7) is capable of generating and outputting acontinuous stream of supercells. This data stream consists only ofordered sets and proprietary formatted 60-byte cells. Cells that arereceived by a switching ASIC for transmission are inserted into a cellslot within this output stream of supercells. When a 60-byte formattedATM cell is not available for transmission, either an empty cell or oneor more Idle Ordered Sets are inserted, since both represent unusedbandwidth.

As discussed above, since some interface cards 21 require a standardtiming reference, the system of the present invention provides means fordistributing system timing throughout the switching fabric. Any UCS inan peripheral shelf 3A, 3B, etc., can contain an interface card 21 whichacts as a reference clock source (eg. a T1 interface). If a card ischosen to be a reference clock source, it will be enabled to transmitits clock signal to the local hub card 23 via a backplane linedesignated as ESYNC. AU interface cards 21 share this line to the hubcard 23, and only drive the line if enabled. The ESYNC signal receivedby hub card 23 is distributed to the rest of the system as an ETOSsignal (Table I) via the switching fabric. The ETOS signal is routedthrough the system to a System Synchronization Unit (SSU), which usesthe received EROS signal to generate STOS from the ETOS timingreference. The STOS signal is then re-distributable throughout thesystem, for receipt of STOS by any card in the system. The SSU receivesthe ETOS reference clock signal via the switch fabric drop bus 27. Inthis way, the reference clock signal can reach the systemsynchronization unit (SSU) regardless of where the SSU is located.

Synchronous and asynchronous transmission interfaces can both be used toprovide reference clocks. Synchronous interfaces inherently containreference timing in the interface's data signal. Asynchronous interfacescan contain reference timing in the form of the PLCP frame rate, whichhas no relationship to the physical data rate of the interface. Anasynchronously provided reference clock usually contains considerablejitter, typically at 8 Khz, but this can easily be filtered out by theSSU. Examples of synchronous interfaces would be E1 and T1; E3 and T3carry reference timing either asynchronously or synchronously.

As discussed above, the system synchronization unit (SSU) is responsiblefor generating the system clock STOS from the selected reference clockETOS. The SSU is essentially a very stable PLL, coupled with controllogic to allow selection of different reference sources, and additionallogic to minimize system clock perturbations that might occur duringreference clock changes or failures. The PLL comprises a DAC, VCXO,phase comparator in feedback configuration, in the usual manner.

Distribution of the system clock is accomplished via the switchingfabric, providing distribution to all interface cards 21 withoutrequiring a dedicated clock network. The mechanism by which this is doneis the aforementioned Ordered Set (OS). As discussed above, an OrderedSet (OS) comprises 32 bits of data which are transmitted on the drop bus27. The OS is uniquely identified by a corresponding Ordered SetIndicator (OSI) pulse. A single bit in the 32 bit data pattern indicatesif the OS is also a System Timing OS (STOS), a special case of OS whichis the equivalent of a rising edge of an 8 Khz clock pulse.

The same mechanism is used by hub cards 23 in order to transmit thereference clock from an interface card 21 to the SSU. In this case asingle bit in the OS pattern is used to indicate if the OS is also anESYNC Timing OS (ETOS), which is a special case of an OS which is theequivalent of a rising edge of an 8 Khz reference clock pulse.

In the event that the system and reference clock signals experiencesimultaneous rising edges, the STOS and EROS must occur simultaneously.This is possible within a single OS by asserting both the STOS and ETOSbits, therefore the switching fabric is capable of distributing multipleclock signals simultaneously.

Due to the flexibility of the reference clock and system clockdistribution method, the location of the SSU within the system is alsovery flexible. The SSU must be located within an peripheral shelf 3A,3B, etc., but there is no restriction as to which peripheral shelfwithin the system contains the SSU, unless the configuration matrix isnot a non-blocking one. The SSU can be located on any hub card 23, orcan be located on a dedicated card that is installed in a UCS slot.

Distribution of ETOS and/or STOS timing signals through a multi-stageswitching core can be accomplished in many ways. FIG. 16 shows apossible distribution scenario in the 32×32 switching core 1 (depictedhere in stages 1A, 1B, etc.). Note that it is sufficient for only one ofthe ISLs to carry TOSs out of the first and second stages 1A and 1B ofthe switch.

Modifications and alternative embodiments of the invention are possiblewithin the sphere and scope of the invention as described herein.

We claim:
 1. A communication system comprising:a) a hub slot forreceiving any one of a plurality of hub cards for receiving andtransmitting data cells; b) a plurality of universal card slots; c) aplurality of interface cards insertable into any one of said pluralityof universal card slots for receiving incoming ones of said data cellscontaining data and transmitting outgoing ones of said data cellscontaining data; d) an add bus having respective data links connectedbetween individual ones of said universal card slots and said hub slotfor receiving said outgoing ones of said data cells from said pluralityof interface cards and transmitting said outgoing ones of said datacells to said one of said plurality of hub cards; e) a drop bus having asingle data link connected between all of said universal card slots andsaid hub slot for transmitting said incoming ones of said data cellsfrom one of said plurality of hub cards to said plurality of interfacecards; and f) means within each of said interface cards for filteringsaid incoming ones of said data cells from said drop bus and therebyrouting said data cells to an appropriate one or more of said pluralityof interface cards.
 2. The communication system of claim 1, wherein atleast one of said plurality of hub cards comprises an internalcommunication path between said add bus and said drop bus.
 3. Acommunication system comprising:a) a hub slot for receiving any one of aplurality of hub cards for receiving and transmitting data cells; b) aplurality of universal card slots; c) a plurality of interface cardsinsertable into any one of said plurality of universal card slots forreceiving incoming ones of said data cells containing data andtransmitting outgoing ones of said data cells containing data; d) an addbus having respective data links connected between individual ones ofsaid universal card slots and said hub slot for receiving said outgoingones of said data cells from said plurality of interface cards andtransmitting said outgoing ones of said data cells to said one of saidplurality of hub card; e) a drop bus having a single data link connectedbetween all of said universal card slots and said hub slot fortransmitting said incoming ones of said data cells from one of saidplurality of hub cards to said plurality of interface cards; and f)means within each of said interface cards for filtering said incomingones of said data cells from said drop bus and thereby routing said datacells to an appropriate one or more of said plurality of interfacecards; wherein at least one of said plurality of hub cards furthercomprises a plurality of first inputs connected to respective data linksof said add bus, a second input connected to a switching means, a firstoutput connected to said drop bus and a second output connected to saidswitching means, for receiving and concentrating said outgoing ones ofsaid data cells into a high-speed output data stream for receipt by saidswitching means and for receiving a high-speed input data stream fromsaid switching means and applying said high-speed input data stream tosaid drop bus for receipt by said appropriate one or more of saidinterface cards.
 4. The communication system of claim 3, wherein saidswitching means comprises a high-speed data link between said secondoutput and said second input of said one of said plurality of hub cards.5. The communication system of claim 3, wherein said switching meanscomprises a cell switching core having at least one input thereofconnected to said second output of said one of said plurality of hubcards and at least one output thereof connected to said second input ofsaid one of said plurality of hub cards.
 6. A communication systemcomprising:a) a plurality of interconnected universal card slots; b) aplurality of interface cards and control cards insertable into saiduniversal card slots for receiving incoming ATM cells containing routinginformation and either data or control and diagnostic information,respectively, and transmitting outgoing ones of said ATM cellscontaining routing information and either data or control and diagnosticinformation, respectively; c) means within each of said interface cardsand control cards for pre-pending to said outgoing ones of said ATMcells a plurality of additional header bytes to provide multiple systemfunctions in addition to ATM cell routing in accordance with saidrouting information; and d) means for receiving said outgoing ones ofsaid ATM cells, filtering said additional header bytes and in responseimplementing predetermined ones of said multiple system functions. 7.The communication system of claim 6, wherein one of said multiple systemfunctions comprises selective point-to-point or point-to-multipointrouting of said outgoing ones of said ATM cells within said system. 8.The communication system of claim 6, wherein one of said multiple systemfunctions comprises in-band control and diagnostics.
 9. Thecommunication system of claim 6, wherein one of said multiple systemfunctions comprises priority queuing of said ATM cells.
 10. Thecommunication system of claim 6, wherein one of said multiple systemfunctions comprises simplified ATM cell egress statistics gathering. 11.The communication system of claim 6, wherein one of said multiple systemfunctions comprises error detection across said ATM cells and pre-pendedadditional header bytes.
 12. A communication system comprising aplurality of series connected peripheral shelves, each of saidperipheral shelves having a hub card, an add bus connected to said hubcard and a drop bus connected to said hub card, wherein at least one ofsaid plurality of series connected peripheral shelves has at least aninput for receiving high speed data from at least an adjacent one ofsaid peripheral shelves, and at least an output for transmitting highspeed data to said at least adjacent one of said peripheral shelves,wherein said hub card includes an input for receiving data fromrespective links of said add bus, and an output for transmitting data tosaid drop bus.